Write Verilog Code for a 6 Bit Adder Using a Full 1 Bit Adder Modules

Hello Everyone👋, Welcome back. In our previous blog, we have discussed the installation process of ModelSim and Notepad++. In this blog, we will discuss Hierarchical Modeling Concepts, Module Syntax, and Design of N-bit Wide Adder using Verilog HDL.

Before we discuss the details of Verilog language, we must first understand basic hierarchical modeling concepts in digital design. The designer must use a good design methodology to do efficient Verilog HDL based-design.

1. Hierarchical Modeling Concepts

1.1 Design Methodologies:

There are two basic types of digital design methodologies:

• Top-down design methodology
• Bottom-up design methodology

Top-down design methodology:

In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we came to leaf cells, which are the cells cannot further be divided as shown below.

Figure 1:Top-down design methodology

Bottom-up design methodology:

In a bottom-up design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks. These cells are then used for higher-level blocks until we build the top-level block in the design. Below figure shows bottom-up design process.

Figure 2:Bottom-up design methodology

2. Module syntax

We now relate these hierarchical modeling concepts to Verilog. Verilog provides the concept of module. A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality that is used at many places in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. This allows the designer to modify module internals without affecting the rest of the design.

Let's see the module syntax.

module <module_name> (<module_terminal_list>); ..... <module internals> ..... ..... endmodule          

In order to clear this concept let's take an example of Adder as shown in the figure below.

3. Design of 2-bit, 4-bit, 8-bit, 16-bit,….N-bit wide Adder

The steps required to design any Integrated Chip are:

1. Understand the Logic.
2. Design of Hardware.
3. Converting hardware into Verilog HDL code.

3.1 Design of Full Adder:

Now let's see the design of Full Adder truth table, architecture, Verilog HDL code, and results. As we all know the boolean expressions for sum=a xor b xor cin, cout=ab+bcin+cina.

Figure 3: Truth Table of Full Adder

Now let's see the architecture of Full Adder as shown below.

Figure 4: Architecture of Full Adder

Here is the Verilog HDL code for Full Adder as shown in the figure below:

module Full_Adder(cout,sum,a,b,cin); input a,b,cin; output cout,sum;  xor G1 (sum,a,b,cin); and G2 (G2_out,a,b); and G3 (G3_out,b,cin); and G4 (G4_out,a,cin); or  G5 (cout,G2_out,G3_out,G4_out);  endmodule  //I saved this file as Full_Adder.v (used to write .do file).          

Now let's see how to verify our design (Full Adder) using ModelSim. Before executing the code in modelsim we need another file of code which is known as Testbench.

Here is a question for you what is the purpose of Testbench🤔?

A testbench is a program written in any language for the purposes of exercising and verifying the functional correctness of the hardware model as coded. In our case, Verilog is going to be used for both the model and the test code. The instantiated component on our test generates outputs as I would in the actual case.

Let's see the testbench for Full Adder as shown in the figure below:

module tb; reg a,b,cin; wire cout,sum; integer i; Full_Adder g1(cout,sum,a,b,cin);//Instantiation of DUT design initial     begin 		for(i=0;i<=7;i=i+1) 		begin 		{a,b,cin}=i; 		#1; 		$display("a=%d b=%d cin=%d -> binary_sum=%b -> decimal_sum=%d", 		          a,b,cin,{cout,sum},{cout,sum}); 		end 		end endmodule	      //I saved this file as testbench.v (used for .do file)          

In order to execute Verilog HDL files we need one more file called as .do file.

Let's see .do file for Full Adder design as shown below.

vlib work vlog Full_Adder.v //File name of DUT. vlog testbench.v  //File name of testbench vsim work.tb      //"tb" is module name of testbench run -all  //This file should be save as .do file //Example: adder.do ---> <anyname>.do          

After saving .do file right click on .do file and click Current Dir. Path to Clipboard. Now open Modelsim tool and give commands as shown below:

Modelsim> cd {press ctrl+v} Modelsim> do <.do file name> //For our example: do adder.do          

The results for Full Adder that we got are shown below:

Wow!!! our Full Adder is working😍😍.

3.2 Design of 2-bit Adder:

Image we need to add two digit two binary numbers, for example 1+3=4.

Now let's see evaluation and computation process A=1(01), B=3(11), decimal sum(S)=4, binary sum(S)=100(4).

Design of 2-bit adder is nothing but cascading two full adders as shown below:

Figure 5: 2-bit wide Adder

Now let's convert this hardware into Verilog HDL code and Testbench as shown below:

//Code for full adder module Full_Adder(cout,sum,a,b,cin); input a,b,cin; output cout,sum;  xor G1 (sum,a,b,cin); and G2 (G2_out,a,b); and G3 (G3_out,b,cin); and G4 (G4_out,a,cin); or  G5 (cout,G2_out,G3_out,G4_out);  endmodule   //Code for DUT (2-bit adder) module twobit_adder(S,A,B); input [1:0] A,B; output [2:0] S; wire [2:0] S; wire c0; Full_Adder FA1 (c0,S[0],A[0],B[0],1'b0); Full_Adder FA2 (S[2],S[1],A[1],B[1],c0); endmodule  //Code for Testbench module tb; reg [1:0] A,B; wire [2:0] S;  twobit_adder ins(S,A,B); initial     begin 		repeat(5) 		begin 		A=$random; 		B=$random; 		#1; 		$display("A=%b B=%b -> binary_sum=%b -> decimal_sum=%d", 		          A,B,S,S); 		end 		A=3; 		B=3; 		#1; 		$display("A=%b B=%b -> binary_sum=%b -> decimal_sum=%d", 		          A,B,S,S); 		end endmodule          

After executing the design in modelsim we got the results as shown below:

Wow!!! our 2-bit Adder is working😍😍.

3.3 Design of 4-bit Adder:

Design of 4-bit adder is nothing but cascading four full adders as shown below:

Figure 6: 4-bit wide Adder

Let's see the Verilog HDL code and testbench for 4-bit wide Adder as shown below:

//Code for full adder module Full_Adder(cout,sum,a,b,cin); input a,b,cin; output cout,sum;  xor G1 (sum,a,b,cin); and G2 (G2_out,a,b); and G3 (G3_out,b,cin); and G4 (G4_out,a,cin); or  G5 (cout,G2_out,G3_out,G4_out);  endmodule   //Code for DUT(4-bit wide adder) module fourbit_adder(S,A,B); input [3:0] A,B; output [4:0] S; wire [4:0] S; wire c0,c1,c2; Full_Adder FA1 (c0,S[0],A[0],B[0],1'b0); Full_Adder FA2 (c1,S[1],A[1],B[1],c0); Full_Adder FA3 (c2,S[2],A[2],B[2],c1); Full_Adder FA4 (S[4],S[3],A[3],B[3],c2); endmodule  //Testbench for DUT(4-bit wide adder) module tb; reg [3:0] A,B; wire [4:0] S;  fourbit_adder ink(S,A,B); initial     begin 		repeat(5) 		begin 		A=$random; 		B=$random; 		#1; 		$display("A=%d B=%d -> binary_sum=%b -> decimal_sum=%d", 		          A,B,S,S); 		end 		A=15; 		B=15; 		#1; 		$display("A=%d B=%d -> binary_sum=%b -> decimal_sum=%d", 		          A,B,S,S); 		end endmodule          

After executing the design in modelsim we got the results as shown below:

Wow!!! our 4-bit Adder is working😍😍.

Great Job!

This is the beauty of Hierarchical Design🙌😍

The same approach follows for the 8-bit adder, 16-bit adder, and so on up to n-bit wide adder. You try to design an 8-bit adder, 16-bit adder, 32-bit adder, and simulate it. Post your comments if you have tried this. You can find all codes in our github repo.

That's all for the blog. We will meet again with an interesting blog. Until then, stay safe. Cheers..🤞

Write Verilog Code for a 6 Bit Adder Using a Full 1 Bit Adder Modules

Source: https://learnai1.home.blog/2020/08/10/design-of-n-bit-wide-adder/

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